Etch process that resists notching at electrode bottom

ABSTRACT

A semiconductor device is manufactured using a small amount of nitrogen in the gate electrode etch process to minimize notching at the bottom of the electrode. Consistent with one embodiment of the present invention, the gate electrode etch process includes using a plasma-etch and selectively etching into the device layer to form the electrode with its lower sidewalls protected using a relatively small percentage of nitrogen in the plasma gas flow.

FIELD OF THE INVENTION

The present invention is directed generally to a semiconductor method ofmanufacture, and more particularly to such a method involving plasmaetching in the formation of electrodes, such as gate electrodes.

BACKGROUND OF THE INVENTION

The electronics industry continues to strive for high-speed,high-functioning circuits. Significant achievements in this regard havebeen realized through the fabrication of very large-scale integration ofcircuits on small areas of silicon wafer. Integrated circuits of thistype are manufactured through a series of steps carried out in aparticular order. The main objective in manufacturing such devices is toobtain a device which conforms to geographical features of a particulardesign for the device. To obtain this objective, steps in themanufacturing process are closely-controlled to ensure that rigidrequirements, for example, exacting tolerances, quality materials, andclean environment, are realized.

Semiconductor devices are used in large numbers to construct most modernelectronic devices. To increase the capability of such electronicdevices or to decrease the costs per die in a competitive market, largernumbers of such devices are integrated into a single silicon wafer. Asthe semiconductor devices are scaled down (i.e., made smaller) toaddress these needs, the structure of the devices and fabricationtechniques used to make such devices must be refined to removecontaminants and tighten tolerances on acceptable structuralimperfections.

A wide variety of processing techniques may be employed in manufacturingsilicon integrated circuit devices, such as chips. In those devices,silicon is employed as a semiconductor for conduction of electricity.The chip manufacturing process typically begins with a silicon wafersubstrate. The silicon wafer substrate is formed of single-crystalsilicon (Si).

Typical steps in the manufacturing process of a silicon integratedcircuit device include growing a layer of silicon dioxide (SiO₂, or“oxide”) upon the surface of the wafer. Silicon dioxide (or otherdielectrics) serves as an insulative material and is often used toseparate various semiconducting layers of integrated circuit devices. Avariety of methods may be employed to force oxide growth on the wafer,including, for example, thermal oxidation. In thermal oxidation, thesilicon reacts with oxygen to form a continuous layer of high-qualitysilicon dioxide. A film of silicon dioxide can also be formed on thesurface of a wafer in other manners. Amorphous or polycrystallinesilicon is then deposited on the oxide. For simplicity, these films willbe referred to as “polysilicon” here. An organic or inorganicanti-reflective coating (ARC) film may be deposited on top of thepolysilicon to improve control of the photolithography process. Avariety of techniques, including, for example, photolithography, may beemployed to achieve desired wafer surface configurations.

In photolithography, a photoresist material, for example, aphoto-sensitive polymer, may be layered atop a somewhat uniformpolysilicon or ARC layer on a wafer surface. A mask having a desireddesign of clear and opaque areas may then be positioned atop thephotoresist layer. A resulting characteristic of photoresist response toUV light permits the photoresist to be selectively subjected to UV lightand then developed to leave behind an image that will serve as a maskfor forming particular patterns of photoresist material atop thepolysilicon or ARC. Once a particular pattern of photoresist is formedatop the polysilicon or ARC of a wafer, portions of the wafer topped bypolysilicon or ARC but not topped by photoresist may then be etched awayfrom the wafer surface.

Etching is a common procedure employed in manufacture of siliconintegrated circuit devices. In general terms, etching is a process bywhich portions of the wafer surface may be selectively removed from thewafer. The etch process yields a layer on the wafer surface having adesired geographical arrangement for further processing. After the etch,the photoresist is removed by a subsequent processing step, leaving thesilicon wafer topped only by select configurations of polysilicon orARC.

The general silicon dioxide/polysilicon/ARC/photoresist/etch methoddescribed above is often used in the formation of the gate electrodeportion of a transistor. Such gate electrode formation involves layeringan oxide, followed by a conductive polysilicon layer, over theunderlying (typically doped) silicon used to form the active andisolation regions. The portions of the conductive polysilicon layerdesignated to form the resultant gate electrodes are hardmasked, forexample, using SiON. Gate electrodes are then formed by selectivelyetching the conductive polysilicon in such a manner that trenches areformed between adjacent gate electrodes. Selectively etching in thiscontext refers to etching the unmasked material, thereby providing atrench with substantially vertical sidewalls.

The ideal selective etching process would provide perfectly verticalsidewalls that provide an interface at the trench bottom which isnormal. In practice, however, process changes made to increasesilicon-to-oxide selectivity result in notching at the bottom of thegate electrode. FIG. 1 illustrates this notching effect at the bottom ofthe pillar-like electrode structures.

In modern semiconductor applications, the thickness of the underlyinglayer of gate oxide has been reduced to about 30 Å for 0.15 micron andsimilar technologies. In the future, the gate oxide layer will bethinned further, perhaps to as little as 15-20 Å. Due to the notchingproblem described above, the plasma etch process conventionally used todefine the gate electrode inevitably consumes some of this oxide;consequently, process changes are made to boost silicon-to-oxideselectivity to minimize the loss. In the prior art, changes such asreducing bias power have been found to be useful for improvingselectivity, but with the disadvantage of lateral etching beginning tooccur as the sidewall protection of the gate electrode is diminished.This lateral etching typically appears as a notch at the gate/oxideinterface.

Accordingly, there is a need to improve the process of forming the gateelectrode in a manner that overcomes the aforementioned deficiencies.

SUMMARY OF THE INVENTION

Generally, the present invention relates to a semiconductor devicemanufactured using a more accurate gate-electrode formation process.Consistent with the present invention, a semiconductor device is formedas part of a wafer having an upper surface, with at least one devicelayer over the upper surface of the wafer. The device layer is formedusing a silicon-to-oxide selectivity during gate etch to improvesidewall protection and to eliminate notching at the bottom of the gateelectrode. In connection with the one embodiment of the presentinvention, it has been discovered that adding a small amount of nitrogenduring the endpoint step prevents the notch without affectingselectivity. A more specific embodiment of the present inventionprovides a method for improving sidewall protection and preventing notchformation without affecting silicon:oxide selectivity. During theendpoint step, a small amount of nitrogen is added to the conventionalpolysilicon etch chemistry.

In accordance with another embodiment of the present invention, aprocess of forming a semiconductor device, includes: forming at leastone device layer over a wafer surface; providing a mask over a portionof the device layer; using a plasma-etch and selective etching into thedevice layer to form a pillar structure having at least one sidewall,the selective etching includes the use of nitrogen as part of the plasmaetch.

Yet another embodiment of the present invention is directed to a processof forming a semiconductor device, comprising: forming at least onedevice layer over an underlying dielectric layer, the device layer andthe underlying dielectric layer being over a wafer surface, providing amask over a portion of the device layer; a step of using a plasma-etchof a first chemistry and selectively etching into the device layer for afunction of forming a pillar structure having at least one sidewall.After the step of using the first chemistry, using a step of using aplasma-etch of a different second chemistry that includes less thanabout ten percent nitrogen of gas flow in the second chemistry for afunction of completing the selective etching upon etching up to theunderlying dielectric layer. In another embodiment, the second chemistryincludes less than about five percent of the gas flow.

In another embodiment, a process of forming a semiconductor deviceincludes forming at least one gate electrode layer over a gate oxide;providing a hardmask over a portion of the device layer; using aplasma-etch of a first chemistry that includes HBr and selectivelyetching into the device layer to form a pillar structure having at leastone sidewall. After using the first chemistry, a plasma-etch of adifferent second chemistry that includes HBr and nitrogen andselectively etching into the device layer to form a pillar structurehaving at least one sidewall is used. The second chemistry includesusing nitrogen in an amount less than about ten percent of gas flow ofthe second chemistry and terminating the use of a plasma-etch of thesecond chemistry in response to reaching the gate oxide. The firstchemistry can include HBr/Cl₂, HBr/HCl, or HBr/Cl₂/Cl₄ for etchingthrough the polysilicon, and can also include a selectivity booster suchas He—O₂.

The above summary of the present invention is not intended to describeeach illustrated embodiment or every implementation of the presentinvention. The figures and the detailed description which follow moreparticularly exemplify these embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be more completely understood in consideration of thefollowing detailed description of various embodiments of the inventionin connection with the accompanying drawings, in which:

FIG. 1 illustrates an actual cross-sectional view of a conventionalsemiconductor device in which gate electrode lines illustrate thenotching issue addressed by the present invention;

FIG. 2 illustrates a cross-sectional sketch of a semiconductor device inwhich gate electrode lines are formed in accordance with an exampleembodiment of the present invention; and

FIG. 3 illustrates an actual cross-sectional view of a semiconductordevice in which gate electrode lines are formed in accordance with anexample embodiment of the present invention.

While the invention is amenable to various modifications and alternativeforms, specifics thereof have been shown by way of example in thedrawings and will be described in detail. It should be understood,however, that the intention is not to limit the invention to theparticular embodiments described. On the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF VARIOUS EMBODIMENTS

The present invention is believed to be applicable to a number ofsemiconductor devices which are manufactured using an electrode etchingprocess. The invention has been found to be particularly advantageous inapplication environments where it is desirable to form gate electrodesover gate oxide layers that are relatively thin, for example, less thanabout 50 Å, and in other applications, less than about 30 Å. For furtherreductions in thickness of the gate oxide layer, the recognizablecontributions in using various embodiments of the present inventionincrease significantly. While the present invention is not necessarilylimited to any particular applications of this type, an appreciation ofvarious aspects of the invention is best gained through a discussion ofvarious application examples of processes used to form suchsemiconductor devices.

Generally, the exemplary processes discussed below illustrate a varietyof techniques for forming a semiconductor device in which a polysilicongate electrode is formed over a thin underlying dielectric layer, suchas a gate oxide, using a plasma etch process that significantly retardsnotching as the plasma etch approaches the endpoint, i.e., the thinunderlying dielectric layer. According to one embodiment, a plasmaetching process used to form the gate electrode includes includes aplasma containing a selected amount of nitrogen in the overall gas flowto provide a desired retardation of notching near the thin underlyingdielectric layer.

Referring to FIG. 2, a cross-sectional view of a portion of asemiconductor device 10 shows polysilicon gate electrodes at lines 20between an overlying hardmask 22 and an underlying dielectric layer 24such as an oxide. The dielectric layer 24 resides over a silicon waferregion 26 that is used in forming the source/drain and channel regions(not shown) of the transistors including the gate electrodes 20. The gapbetween the gate electrodes 20 is a trench formed using a plasma etchchemistry that provides little if any notching at the trench bottom.

In one particular example application, two different plasma chemistriesare used to retard the notching effect at the bottom of the trench. Thefirst chemistry is a conventional chemistry for selectively etching intothe gate electrode material and not into the mask atop the gateelectrode material. For example, using a hardmask such as SiON, thefirst chemistry can include HBr/Cl₂, HBr/HCl, or HBr/Cl₂/Cl₄, forselectively etching a polysilicon electrode material. The firstchemistry can also include a selectivity booster such as He—O₂. Afterusing the first chemistry and sometime before reaching the underlyinggate oxide, the chemistry is changed to one that includes a small amountof nitrogen, e.g., less than about twelve to fifteen percent of gas flowin the second chemistry depending on the application. This secondchemistry is used to complete the selective etching, with an endpointdetection process or other technique used to terminate thisnitrogren-modified plasma etch. By adding such an amount of nitrogenbefore the endpoint termination, the notching effect such as shown inFIG. 1 is avoided without affecting the selectivity of the overalletching process.

In another particular example application, the same plasma chemistry isused in the trenching to form the electrode pillar, wherein the benefitof the added nitrogen to retard the notching effect at the bottom of thetrench is realized when the etching approaches the underlying electrodedielectric. Any of the so-called second chemistries, discussed herein,can be used in this process.

Accordingly, an important aspect of the present invention is the use ofa small amount of nitrogen in completing the plasma etching forformation of the gate electrode. In one embodiment, this plasma etchingincludes using less than about ten percent of nitrogen in the plasmachemistry when etching near the underlying electrode dielectric. Forother applications, this amount of nitrogen can vary depending upon thedesired need for retarding the notching effect and/or minimizing anyadverse effect on overall selectivity.

FIG. 3 illustrates an actual cross-sectional view of a semiconductordevice in which gate electrode lines are formed, according to an exampleembodiment of the present invention, using nitrogen in an amount ofabout two percent (specifically, 1.7 percent) of the total plasma gasflow. In this example embodiment, the silicon etching tool being used isa Lam Research Corp. TCP 9400SE silicon etch tool, and using SiON as ahardmask atop the portions of the polysilicon to be used in forming thepillar electrode structures. For reliable control of such low flowrates, rather than using a pure N₂ as the nitrogren additive, a dilutedgas mixture such as 80% helium/20% nitrogen (He—N₂), may beadvantageous.

The amorphous silicon and thermal oxide etch rates and selectivitieswith and without nitrogen are shown below in Table I usingphotoresist-patterned wafers for measurements. Nitrogen addition has asmall impact with the difference (e.g., 5% or less) well within themeasurement error, and on hardmasked wafers, the oxide etch rate is solow that it is not measurable, giving nearly infinite selectivity.

TABLE I Etch rate and selectivity measurements. No With Delta N₂ added20 sccm N₂ (%) Amorphous silicon etch rate 17.9 18.1 −1% (Å/sec) Thermaloxide etch rate 0.44 0.46 −5% (Å/sec) Silicon:oxide selectivity 40.739.3  3%

The following Table II exemplifies an acceptable chemistry for achievingthe formation of the electrode structure illustrated in FIG. 3:

Hard mask gate etching with N2 addition at end point step BreakthroughBulk Endpoint Over Etch Step 01 Step 02 Step 03 Step 04 Step 05 Step 06Step 07 Step 08 Pressure (mT) 10.00 10.00 20.00 20.00 80.00 80.00 90.000.00 RF — Top (W) 0.0 350.0 0.0 150.0 0.0 250.0 0.0 0.0 RF — Bottom (W)0.0 50.0 0.0 30.0 0.0 70.0 0.0 0.0 Gap (cm) 8.100 8.100 8.100 8.1008.100 8.100 8.100 8.100 Cl2 (sccm) 0.0 0.0 10.0 10.0 0.0 0.0 0.0 0.0 HBr(sccm) 0.0 0.0 150.0 150.0 200.0 200.0 0.0 0.0 80%He—O2 (sccm) 0.0 0.015.0 15.0 10.0 10.0 0.0 0.0 CF4 (sccm) 100.0 100.0 0.0 0.0 0.0 0.0 0.00.0 He (sccm) 0.0 0.0 0.0 0.0 200.0 200.0 200.0 0.0 N2 (sccm) 0.0 0.03.0 3.0 0.0 0.0 0.0 0.0 He damp (T) 8.0 8.0 8.0 8.0 8.0 8.0 0.0 0.0Completion Stabl Time Stabl EndPt Stabl Time Time End Time 30 8 30 15030 60 7 Channel A Delay (sec) 40 Norm (sec) 1 Trigger (%) 99Temperatures (° C.) Bottom Electrode 65.0 Chamber 60.0 ChannelWavelength (nm) A 405 B 520 MFC Gas sccm 1 Cl2 200 2 HBr 200 3 80%He—O220 4 CF4 200 5 He 200 6 SF6 100 7 O2 100 8 N2 50

The present invention is applicable to fabrication of various types ofelectrodes having an underlying thin dielectric layer that reacts to thenitrogen plasma additive in the same manner as oxide. The presentinvention should not be considered limited to the particular examplesdescribed above, but rather should be understood to cover all aspects ofthe invention as fairly set out in the attached claims. Variousmodifications, as well as numerous structures to which the presentinvention may be applicable, will be readily apparent to those of skillin the art upon review of the present specification. The claims areintended to cover such modifications and devices.

What is claimed is:
 1. A process of forming a semiconductor device,comprising: forming at least one gate electrode layer over a gate oxide,the gate oxide being above a wafer surface; providing a hardmask over aportion of the device layer; using a plasma-etch of a first chemistrythat includes one of HBr/Cl₂, HBr/HCl, or HBr/Cl₂/Cl₄, and also includesa selelivity booster, and selectively etching into the device layer toform a pillar structure having at least one sidewall; after using thefirst chemistry, using a plasma-etch of a different second chemistrythat includes HBr and nitrogen and selectively etching into the devicelayer to form a pillar structure having at least one sidewall, thesecond chemistry including nitrogen in an amount less than about tenpercent of gas flow of the second chemistry, wherein the amount ofnitrogen is maintained to minimize notching in the pillar structurewithout affecting selectivity; and terminating the use of a plasma-etchof the second chemistry in response to reaching the gate oxide.
 2. Aprocess, according to claim 1, wherein the first chemistry includesHBr/Cl₂ and He—O₂.